1. Executive Summary and Selection Criteria

In the technology landscape of September 2026, the distinction between a consumer laptop and a mobile AI workstation does not lie in the accelerator’s theoretical TFLOPS, but in three metrics that are often confused and which should be distinguished from the outset: the memory capacity (how many gigabytes the system can address), the bandwidth (how fast it can transfer that data) and the context size (how many tokens the inference engine can handle simultaneously). A laptop may have 128 GB of unified memory, yet still suffer a drop in performance if its bus cannot keep up; similarly, a context of one million tokens is useless if the machine does not have sufficient memory to store the associated KV cache.

The consolidation of models such as Llama 4 in its Scout variant, with a declared context window of 10 million tokens, and DeepSeek-V4.1-Flash for efficiency and encoding workloads, has shifted the bottleneck from computation to the memory hierarchy. The unified memory architecture (UMA) allows the CPU, GPU and NPU to access the same address space without intermediate copies via the PCIe bus, thereby reducing access latency and avoiding the duplication of tensors between VRAM and system RAM.

It is also worth highlighting a distinction that determines the actual feasibility of each workload: running a dense model is not the same as running one with a MoE (Mixture of Experts) architecture. An MoE model with a high total number of parameters keeps only a fraction of its parameters active for each token, meaning that its requirements for calculation per token are considerably lower than those of a dense model of the same nominal size. However, their requirements for memory capacity They are still determined by the total number of parameters, because all the experts must be stored in memory in order to be selected. It is this asymmetry that explains why certain large models can run locally at acceptable speeds but, conversely, require a level of memory capacity that few mobile devices can match.

2. Computing Architectures: CPU, GPU and NPU

Modern architecture has moved beyond computing based solely on discrete GPUs. Today’s SoCs integrate NPUs specifically designed for reduced-precision inference operations (INT8, INT4) and computing engines that accelerate formats such as native FP8. For sustained workloads, hardware selection should prioritise memory bandwidth over core clock speed, given that language model inference is a data-intensive workload rather than one based purely on arithmetic operations.

2.1. Unified Memory: capacity, bandwidth and context

Direct memory access is the criterion that best distinguishes between systems. Architectures that separate VRAM from system RAM incur latency penalties every time a tensor has to cross the PCIe bus; this penalty is exacerbated in autoregressive decoding pipelines, where the model iterates through its weights once per token generated.

LPDDR5X memory has become established during 2026 as the foundation of high-end mobile platforms, with buses in the highest-capacity devices reaching 512-bit configurations to increase the available bandwidth. The practical recommendation is not to set an absolute number of bus bits as a ‘minimum standard’, but rather to calculate the required bandwidth based on the model to be run: as a general rule, memory bandwidth in GB/s directly determines the rate of token generation per second, and a machine whose bandwidth is insufficient for the size of the active model will suffer noticeable performance degradation.

With regard to context, a model whose declared window spans one million tokens requires memory to be reserved for the key-value cache (KV cache), the size of which grows approximately linearly with the length of the context and depends on the number of layers and attention heads in the model. It is a common mistake to attribute the ability to handle large contexts solely to bus speed: without sufficient physical memory, the model’s declared window is unachievable in practice.

The table above contains only figures published by the manufacturers and verifiable in their official specifications. It should be regarded as indicative: the effective bandwidth during sustained inference also depends on the device’s thermal management and the power distribution between the CPU, GPU and NPU; therefore, it does not automatically translate into a figure for tokens per second without a direct measurement of the specific model and its quantisation.

3. Workload Analysis

For an AI developer in 2026, the workflow is structured around three pillars, each with markedly different requirements:

• Inference on heavy models: The required memory capacity is determined by the parameters totals of the model, not by the assets. In MoE architectures such as Qwen3.8-Max, classified as a MoE with a total of 2.4 trillion parameters, the model activates a subset of experts per token, which reduces the computational load required; however, all of the experts must remain resident in memory. With INT4 quantisation, the rule of thumb is approximately one byte for every two parameters, so 64 GB of unified memory can accommodate models with between 100 and 130 billion total parameters, not a model with significantly more parameters. Sizing the hardware based on the number of parameters assets This is the most common mistake and leads to people buying machines that are unable to load the desired model.
• Fine-tuning (LoRA/QLoRA): The NPU plays a secondary role here, as training and fine-tuning require the general-purpose computing engine. Native support for FP8 is crucial for reducing effective computation time, and the LoRA and QLoRA techniques allow adaptation layers to be fine-tuned without retraining the entire model. When sizing memory, it is important to consider not only the weight of the quantised base model, but also the optimiser states and activations, which, during fine-tuning, far exceed the requirements of mere inference.
• Computer agents: Proprietary models such as GPT-6 Astra, in its computer-oriented variant, require minimal interrupt latency and deep integration between the NPU and the operating system. The feasibility of running these workloads locally depends both on memory and on the SoC’s ability to maintain concurrent, low-latency inferences whilst the rest of the system remains active.

"The power of an AI workstation in 2026 is not measured by its maximum load capacity, but by its energy efficiency during sustained inference of long-context agentic models." A recurring observation among semiconductor manufacturers throughout 2026.

4. Strategic Recommendations by Profile

4.1. Open-source model developers

If your workflow involves deploying and testing Llama 4 Scout, with a declared context window of 10 million tokens, or Gemma 4 in its 12-billion-parameter variant, you should prioritise systems with at least 128 GB of unified memory. The reason is that, although Gemma 4 12B runs comfortably on 32 GB systems, the amount of memory available determines the effective context window it can sustain and how many models it can keep loaded simultaneously during benchmark testing. Bandwidth is a more decisive factor than the number of CPU cores: look for architectures with wide-bus memory controllers and check the published bandwidth figure rather than the core count.

4.2. Prompt engineering and agent integration

For those working with multimodal models such as Qwen3.8-Omni-Flash, the NPU plays a significant role. Offloading vision and audio tasks to the NPU frees up the main computing engine for token generation, which, in certain multimodal pipelines, results in a noticeable improvement in the application’s overall performance. However, this improvement depends on the support provided by the software stack: there is no universal multiplier applicable to any combination of hardware and model; rather, the benefit must be measured against the specific pipeline.

5. Conclusion: The ROI of Hardware Architecture

Investing in AI hardware in 2026 requires a 24-month outlook. The main risk of obsolescence does not stem from a lack of raw processing power, but from the inability of the memory architecture to support long contexts and models with a high total number of parameters. For this reason, three factors determine the longevity of a mobile development environment: unified memory capacity, effective bandwidth and native FP8 support in the computing engine.

The practical recommendation is to size the hardware according to the expected workload rather than the processor’s technical specifications. For inference on medium-sized open models, 64 GB of unified memory offers a reasonable starting point; for fine-tuning or deploying MoE models with a high total number of parameters, 128 GB is no longer a luxury but a requirement. Verifying the bandwidth published by the manufacturer, checking for actual FP8 support in the software stack, and measuring the generation speed on the specific model to be used provides more information than any theoretical TFLOPS figure.